1. Field of the Invention
The present invention relates to a semiconductor device for realizing a package for stacked package SiP that is thinner and less prone to warp, and to a method of fabricating such a semiconductor device.
2. Description of the Related Art
SiP (System in Package) is receiving attention as a technology for achieving smaller electronic apparatuses having higher functionality. Within SiP, stacked-package SiP (PoP, Package on Package) provides an easy solution to the problem of ensuring that products are defect-free. In addition, stacked-package SiP allows a high degree of freedom in combining chips. As a result, orders for stacked-package SiP are increasing, particularly for portable telephones.
However, stacked-package SiP have the problem of higher assembly height than stacked-semiconductor element SiP in which a plurality of semiconductor elements are stacked in one package. Stacked-package SiP further have the problems of greater package warp and swelling due to the thinning of the interposer substrate and partial molding in which only sites for mounting semiconductor elements are molded.
FIG. 1 is a sectional view showing a typical configuration of a lower package in stacked-package SiP. This package uses built-up circuit board 11 having core layer 12 as an interposer substrate. In this package, moreover, semiconductor element 10, which is a chip, is connected by wire bonding to built-up circuit board 11 by bonding wires 26. This package has a partially molded structure in which only the mounting site of semiconductor element 10 is sealed by sealing layer 14.
Various techniques have been proposed as countermeasures for the height of attachment and package warp.
For example, JP-A-2003-133521 describes a technique for lowering the profile of the assembly. More specifically, JP-A-2003-133521 describes a technique in which a package is fabricated by, rather than mounting a chip on a substrate, providing an opening in the substrate, mounting a chip face-up on a support tape on the bottom of the opening, connecting the chip by wire bonding, implementing partial molding of the chip site, and finally, mounting balls.
Alternatively, JP-A-2005-45251 discloses a technique for fabricating a package by mounting a chip on a substrate, mounting solder balls as external electrodes, molding the entire surface, and then grinding a portion of the solder balls and chip reverse surface.
As a countermeasure for warp of the package, JP-A-2007-42762 discloses a technique of varying the heights of electrodes that are formed on a lower package and that are the connectors with an upper package in order to ensure connection reliability when warp occurs.
Although both lower profile of the assembly height and reduced warp of the package are sought in stacked-package SiP, these two objects are difficult to achieve simultaneously in stacked-package SiP.
In the technique disclosed in JP-A-2003-133521, the thickness of a package is reduced by providing openings in the substrate and mounting semiconductor elements in these openings. However, such a package adopts a partially molded construction only for semiconductor elements, and as a result, warp is difficult to suppress at the ends of the package that are not sealed by molding.
In the technique disclosed in JP-A-2005-45251, a construction in which the entire surface is sealed by molding is realized by mounting a semiconductor element and solder balls on a substrate and then molding the entire surface. However, the reverse surface of the semiconductor element is exposed by grinding, and although the thickness of the package can be reduced, warp in the region of the semiconductor element is difficult to suppress.
In the technique disclosed in JP-A-2007-42762, the problem of connection defects resulting from warp when stacking an upper and lower package is solved by adjusting the height of electrodes on the lower package. However, when reducing the thickness of a substrate to achieve assembly height of a lower profile, warp of the package is difficult to absorb by merely adjusting the height of electrodes. Lower profile of the assembly height and reduced warp are therefore difficult to achieve simultaneously.